1. Field of the Invention
This invention relates generally to an IC tester for testing IC's such as memory IC's, logic IC's, memory IC's having a built-in logic circuit, and particularly to logic comparison for comparing an output response from an IC with an expected value.
2. Background Art
FIG. 1 illustrates a schematic diagram of a prior art IC tester in which an IC to be tested is indicated by 10.
A pattern generating section 11 comprises an algorithmic pattern generator 11A, a random pattern memory 11B, a multiplexer 11C, a control part 11D, a multiplexer 11E, and a comparison control signal generator 11F. The algorithmic pattern generator 11A generates relatively regular algorithmic pattern data AP by a logic operation in synchronism with a clock signal CK from a timing generator 12. The algorithmic pattern data AP is primarily used to generate a pattern to be applied for testing a memory, an address pattern and an expected value pattern. The random pattern memory 11B reads out a prestored random pattern RP in synchronism with the clock signal CK. The random pattern RP is primarily used to generate a pattern to be applied for testing a logic circuit and an expected value pattern. No reference will be made to the generation of the applied pattern and the address pattern, since this invention is particularly concerned with the comparison between a response output from an IC being tested and an expected value.
The multiplexer 11C is supplied with algorithmic pattern data AP from the algorithmic pattern generator 11A and a random pattern RP from the random pattern memory 11B and produces two sequences of pattern data DA and DB each having K bits by either selecting one of the data AP and RP, or combining desired portions of these data AP and RP, or taking a logical AND, a logical OR, or an exclusive-OR of the data AP and RP, in accordance with a control signal MCNT from the control part 11D. The multiplexer 11E selects and outputs the data at a desired bit position of specified one of the two sequences of the pattern data DA and DB to each of the output bit positions of the multiplexer 11E such that the outputs of N bits corresponding to N test channels CH.sub.1 -CH.sub.N are provided as desired expected value signals EXP.sub.1 -EXP.sub.N. This selection is designated by a data selecting signal DSEL and a bit selecting signal BSEL produced at a pin control interface 14. The expected value signals EXP.sub.1 -EXP.sub.N thus output from the multiplexer 11E are provided to logic comparator sections 30.sub.1 -30.sub.N of the corresponding test channels CH.sub.1 -CH.sub.N. Generating the two sequences of the pattern data DA and DB permits the use of those data to compound expected patterns having a greater number of bits than the K bits of each of the data DA and DB, for example.
Although not shown, the multiplexer 11E is equipped therein with registers each corresponding to one of the test channels. Bit selecting signals BSEL (plural bits) and data selecting signals DSEL (one bit) are set in those registers, and for each of the individual test channels, data at a specified bit position of the data DA or DB as specified by those select signals having been set are output as expected value signals.
Connected to N terminal pins of an IC 10 to be tested are level/timing comparator sections 20.sub.1 -20.sub.N of N test channels CH.sub.1 -CH.sub.N, respectively. The outputs of the level/timing comparator sections 20.sub.1 -20.sub.N are connected to logic comparator sections 30.sub.1 -30.sub.N. It is noted that the suffixes of the reference numerals 20 and 30 and the reference symbols CH and EXP represent the channel number. Each level/timing comparator section, say the comparator section 20.sub.1 and the associated logic comparator section 30.sub.1 constitute one test channel. When any one of the channels is representatively described in the following descriptions, the suffix representing the channel number may be omitted. Each level/timing comparator section 20 logically determines the output from a corresponding pin of the IC 10 under test at the timings of strobes STRB1 and STRB2 from the timing generator 12.
The logic comparator sections 30.sub.1 -30.sub.N are each equipped with exclusive-OR circuits XOR1 and XOR2 for detecting a non-coincidence, and AND gates AND1 and AND2 for controlling the outputs of the detected results. One of the input terminals of each of the exclusive-OR circuits XOR1 and XOR2 is provided with the logically determined output of the associated one of the level/timing comparator sections 20.sub.1, 20.sub.2, 20.sub.N while the others of the input terminals of the exclusive-OR circuits XOR1 and XOR2 are connected in common to be provided with the expected value signals EXP.sub.1 -EXP.sub.N. If the result of logic decision and the expected value are in coincidence, an L level is output, and if they are not in coincidence, an H level is output.
The comparison results of the exclusive-OR circuits XOR1 and XOR2 are applied to the AND gates AND1 and AND2, respectively, where it is decided by comparison control signals CPE1 and CPE2 whether or not to output the logic comparison results. The logic comparison results are used to evaluate the defect analysis property of an IC under test or determine the quality thereof, but a further description thereon is omitted as it is not directly related to this invention.
While in FIG. 1, the level/timing comparator sections 20.sub.1, 20.sub.2, . . . 20.sub.N and the logic comparator sections 30.sub.1, 30.sub.2, 30.sub.N . . . are only diagramatically shown, their actual constructions are similar to those shown in U.S. Pat. No. 4,862,071. For example, each comparator section is constructed as illustrated in FIG. 2 for one test channel.
In FIG. 2, each of pin outputs D.sub.0 of the IC 10 under test is compared with a H reference level V.sub.H and a L reference level V.sub.L at the H level comparator 21C.sub.H and L level comparator 21C.sub.L, respectively, of the level/timing comparator section 20. If the output D.sub.0 is higher than the reference level V.sub.H, the outputs of the comparators 21C and 21C.sub.L will be at L and H levels, respectively. If the output D.sub.0 is lower than the reference level V.sub.L, the outputs of the comparators 21C.sub.H and 21C.sub.L will be at H and L levels, respectively. The level comparison outputs of these comparators on the H level side and the L level side are extracted by strobes STRB1 and STRB2 of different timings, respectively in the strobe circuits 21S H level side and in the strobe circuits 21S.sub.H1 and 21S.sub.H2 and the strobe circuits 21S.sub.L1 and 21S.sub.L2, respectively. That is, the results of logic decision at particular timings are sampled, and the sampled logics are logically compared with the excepted values EXP and their inverted logics in the AND circuits 31.sub.H1 and 31.sub.H2 and in the AND circuits 31.sub.L1 and 31.sub.L2. In this example, on either of the H logic side (21.sub.C.sub.L, 21S.sub.L1, 21S.sub.H2, 31.sub.H1, 31.sub.H2) and the L logic side (21C.sub.L, 21S.sub.L1, 21S.sub.L2, 31.sub.L1, B1.sub.L2), L level outputs are generated if the sampled logics are correct ones, so that if the expected value EXP is at the H level, the AND circuits 31.sub.H1, 31.sub.H2 and the AND circuits 31.sub.L1, 31.sub.L2 will generate L level outputs. When the expected value EXP is at the L level as well, the AND circuits 31.sub.H1, 31.sub.H2 and the AND circuits 31.sub.L1, 31.sub.L2 will generate L level outputs if the sampled logics are correct ones. The AND circuits 31.sub.H1, 31.sub.H2 and the AND circuits 31.sub.L1, 31.sub.L2 act to control in accordance with the control signals CPE1 and CPE2 whether or not to output the comparison results. As illustrated in FIG. 2, the test channels are so arranged that the H logic tests and L logic tests may be conducted separately and that logic tests may be carried out at two different timings for each of the Hand L logics. It is noted that the strobe circuits ST1 and ST2 of each of the test channels diagramatically shown in FIG. 1 correspond to the level comparators 21C.sub.H and 21C.sub.L and the strobe circuits 21S.sub.H1, 21S.sub.H2 and 21S.sub.L1, 21S.sub.L2 shown in FIG. 2. The exclusive-OR circuits XOR1 and XOR2 of FIG. 1 correspond to the AND circuits 31.sub.H1, 31.sub.H2, 31.sub.L1, 31.sub.L2 of FIG. 2. The AND gates AND1, AND2 of FIG. 1 correspond to the AND gates 32.sub.H1, 32.sub.H2, 32.sub.L1, 32.sub.L2 of FIG. 2.
Further, the arrangements are such that the comparison results obtained with the strobes STRB1 and STRB2 may be taken separately from OR gates 33S1 and 33S2, as required. The outputs of the second strobe circuits 21S.sub.H2 and 21S.sub.L2 on the H logic side and L logic side, respectively, are applied to a HAND gate B4, and if the output D.sub.0 of the IC 10 is at neither the H logic level nor the L logic level but goes into a state of high impedance (Hi-Z) at an intermediate level, it is detected to output an L level. Either one of the outputs of the HAND gate 34 and OR gate 33SR is selected by a selector 35. In the Hi-Z state detecting mode, the selector 35 selects the output of the HAND gate 34, and in the mode other than the Hi-Z state detecting mode it is controlled by a mode switching signal Z from a Hi-Z state detecting mode signal generator (not shown) to select the output of the OR gate 33S2. However, since the actual arrangement illustrated in FIG. 2 is not related to the essence of the present invention, reference will be made to the simplified drawing of FIG. 1 in the following descriptions.
As indicated above, in the prior art the comparison control signals CPE1 and CPE2 are applied to the AND gates AND1 and AND2 disposed in each of the logic comparator sections 30.sub.1, 30.sub.2, . . . 30.sub.N to control whether or not to output the logic comparisons. The comparison control signals CPE1 and CPE2 output from the pattern generating section 11 are applied to the the logic comparator sections 30.sub.1, 30.sub.2, . . . 30.sub.N in common, so that the control as to whether or not to enable the logic comparisons may be effected only in the same form with respect to all of the test channels CH.sub.1 -CH.sub.N (and hence all of the pins). In other words, the control can be carried out only as to whether to open the AND gates AND1 to take out the decision results on the exclusive-OR circuit XOR1 side only, or to open the AND gates AND2 to take out the decision results on the exclusive-OR circuit XOR2 side only, or to take out both of the results, in all the logic comparator sections 30.sub.1, 30.sub.2, . . . 30.sub.N.
Incidentally, with the advance of the semiconductor integrated circuits, IC's requiring the various test conditions as will be mentioned below for example have been developed:
(A) As is the case with the multi-bit dynamic RAM or special memory (ASMIC: application specific memory IC), where the respective output pins may differ in their output states (logic output state or HI-Z state) in the respective test cycles, it is required to switch the comparison control signals CPE1 and CPE2 in real time for every individual pin in order to compare the output of the pin with the associated expected value signal.
(B) As in the test for the multi-bit dynamic RAM, it is required to compare only a particular cycle of a particular bit with the associated expected value signal.
(C) In a memory having a built-in logic operation circuit, it is required to control for each of the bits as to whether or not to output the comparison results with respect to the output data of the logic operation circuit.
(D) When each output bit is compared with the associated expected value signal, it is required to switch between the operation of making the comparison for each of the individual channels (that is, each of the individual pins) in real time and the operation of making the comparison for all the channels in common in real time.
With such IC's as mentioned above, there is an inconvenience that it is impossible to test them by the conventional IC tester.
With the conventional IC tester, when a plurality of IC's of the same type are to be simultaneously tested, predetermined one or more output pins of each of IC's 10.sub.1, 10.sub.2, . . . 10.sub.N are connected to test channels CH.sub.1 -CH.sub.N as illustrated in FIG. 3, for example, in a similar manner shown in FIG. 1. In this case, the open and closed states of gates AND1 and AND2 are controlled with respect to all the channels in common. Accordingly, there is a disadvantage that it is not possible to mask in real time only those of the IC's that have been found defective, for example.
Specifically, it is not easy to measure the AC characteristics only at a particular address of each of devices being simultaneously measured or to mask any other device or devices in real time. Although the use of a failure analysis memory would permit real time masking, all of IC testers as used in mass-production factories are not equipped with such failure analysis memories, nor do the IC testers provided with failure analysis memories have necessarily a capacity enough to accommodate all devices for simultaneous measuring thereof. In addition, in the case of a memory device there tends to be a constant relation between the dynamic current flowing through the device and the access time (response speed), so that it is necessary to use different timings for comparison in order to simultaneously measure devices having different access times. Consequently, a single test will not do, but a plurality of tests at the settings of different timings are required.